The present invention relates generally to a semiconductor memory device and a method of operating the same, more particularly relates to a nonvolatile memory device such as a NAND flash memory device.
A memory array in a semiconductor memory device such as a NAND flash memory device includes memory blocks, and each of the memory blocks has plural memory cell strings connected between a common source line and a bit line. Hereinafter, a known NAND flash memory device will be described in detail with reference to accompanying FIG. 1 and FIG. 2.
FIG. 1 is a view illustrating circuit for describing a part of the known NAND flash memory device, and FIG. 2 is a sectional view illustrating schematically a memory cell string of the NAND flash memory device in FIG. 1.
As shown in FIG. 1, the NAND flash memory device includes a memory array 10 having memory cells C[a0:kn] for storing data and a block switch circuit 15 for transferring operation voltages to a selected memory block in the memory array 10.
Referring to FIGS. 1 and 2, the memory array 10 includes a plurality of memory blocks. Only one memory block is shown in FIG. 1. Each of the memory blocks has plural memory cell strings ST[0:k] connected between a common source line SL and bit lines BL[0:k]. Each of the memory cell strings, e.g. ST0 includes a source select transistor SST connected to the common source line SL, a drain select transistor DST connected to the bit line BL0 and memory cells C[a0:an] connected in series between the source select transistor SST and the drain select transistor DST. A gate of the source select transistor SST is connected to a source select line SSL formed over a gate insulating layer 27. A gate of the drain select transistor DST is connected to a drain select line DSL formed over a gate insulating layer 27. The gate insulating layer 27 is formed on the semiconductor substrate 21. Each of the memory cells C[a0:an] comprises the gate insulating layer 27 used as a tunnel insulating layer, a floating gate FG, a dielectric layer 29 and a control gate CG. Here, the gate insulating layer 27 is formed on the semiconductor substrate 21, and the floating gate FG is formed on the gate insulating layer 27, and the dielectric layer 29 is formed on the floating gate FG, and the control gate CG is formed on the dielectric layer 29. The source select line SSL may be formed by using the same conducting layer as the control gate CG, and be connected electrically to a lower layer, which is formed between the source select line SSL and the gate insulating layer 27 and is formed by using the same layer as the floating gate FG, through a contact hole in the dielectric layer 29. The drain select line DSL may be formed by using the same conducting layer as the control gate CG, and be connected electrically to a lower layer, which is formed between the drain select line DSL and the gate insulating layer 27 and is formed by using the same layer as the floating gate FG, through the contact hole in the dielectric layer 29.
The source select transistor SST, the memory cells C[a0:an] and the drain select transistor DST can be electrically connected in series through impurity areas 21S, 21C and 21D formed in the semiconductor substrate 21. The impurity areas includes a source area 21S and a drain area 21D of a memory cell string and cell connection areas 21C. Here, the source area 21S is connected to the common source line SL and the drain area 21D is connected to drain contact DCT. Also, the cell connection areas 21C are formed between gates of the source select transistor SST and an adjacent memory cell Ca0, between each of the memory cells C[a0:an] and between the drain select transistor DST and an adjacent memory cell Can. The drain area 21D may be connected to the bit line BL0 via the drain contact DCT. Insulating layers 23 and 25 are formed between patterns which need to be insulated electrically.
The memory cell strings ST[0:k] in the memory block are connected commonly to the common source line SL, and are arranged in parallel. The memory cell strings ST[0:k] are connected to corresponding bit line BL[0:k], respectively. Gates of the source select transistors SST are connected commonly to the source select line SSL one of a memory block. In addition, gates of the drain select transistors DST are connected commonly to the drain select line DSL of the memory block. Gate of each memory cell C[a0:kn] is connected to corresponding word line WL[0:n], respectively. The source select line SSL, the drain select line DSL and the word lines WL[0:n] connected to the memory array 10 are referred to as local lines.
The block switch circuit 15 applies operation voltages provided through global lines GDSL, GWL[0:n] and GSSL to the local lines DSL, WL[0:n] and SSL of a selected memory block in response to a block select signal BLKSW. The block switch circuit 15 is connected between the global lines GDSL, GWL[0:n] and GSSL and the local lines DSL, WL[0:n] and SSL for the purpose of applying the operation voltages. Additionally, the block switching circuit 15 includes pass transistors NS, N[0:n] and ND driven in response to the block select signal BLKSW. The block select signal BLKSW is enabled in response to row address signals of the control circuit. The operation voltages are generated by a voltage generating circuit, and are provided to the global lines GDSL, GWL[0:n] and GSSL.
High integration of the NAND flash memory device may be achieved by reducing size of the memory cells C[a0:kn] in the memory cell string. However, it is difficult to reduce size of the drain select transistor DST and the source select transistor SST for selecting the memory cell string by size of the memory cells C[a0:kn]. Therefore, high integration of the NAND flash memory device may also be achieved by increasing the number of the memory cells C[a0:an] in the memory cell string ST0. In case of increasing the number of the memory cells in each of the memory cell strings, the number of the drain select transistor DST and the source select transistor SST in a whole memory device may be reduced, but the size of the memory block, i.e., the number of the memory cells in each memory block increases. Since the size of the memory block is limited to the size supported by the control circuit of the NAND flash memory device, it is limited to increase the number of the memory cells in the memory cell string. On the other hand, a method of increasing the number of the memory cell strings may be used as an alternative method for highly integrated NAND flash memory device. In this case, the number of the drain select transistor DST and the source select transistor SST increases. Since it is difficult to reduce the size of the drain select transistor DST and the source select transistor SST by the size of the memory cells C[a0:kn], the size of a chip may increase as the number of the drain select transistor DST and the source select transistor SST increases.